Distributed Arithmetic Based Butterfly Element for Fft Processor in 45nm Technology

ABSTRACT Fast Fourier Transform (FFT) is one of the important signal processing algorithms because of its applications in digital filtering, communication, image processing, spectral analysis and estimation etc. Butterfly computation is the basic operation in the FFT algorithm. In this work, a novel approach is thought of and used in implementing the butterfly element. Distributed Arithmetic Algorithm (DAA) is used to do the butterfly computation instead of using conventional multipliers and adders. This has resulted in a more efficient butterfly element both in terms of area and power. This paper describes the design of such an area efficient butterfly module. Single precision floating point representation is used for the data. This design leads to a lot of area saving and power saving. This butterfly can be used as the basic building block of a low power reconfigurable FFT processor. This finds its application in OFDM based systems and also in software defined radios.